// MEM/WB

// Naming convention for wires into and out
// of this register should be [wirename]3

// In/Out Parameters with # of bits:
// RegWriteSrc = 2
// RegWrite = 1
// ALU = 32
// Mem = 32
// Rw = 5

module Mem_WriteBack(CLK,
                     RegWriteIn,
                     RegWriteOut,
                     RegWriteSrcIn,
                     RegWriteSrcOut,
                     ALUIn,
                     ALUOut,
                     AdderAIn,
                     AdderAOut,
                     MemIn,
                     MemOut,
                     BusBIn,
                     BusBOut,
                     RwIn,
                     RwOut);
  input CLK;    
  input [1:0] RegWriteSrcIn;
  input RegWriteIn;
  input [31:0] ALUIn, AdderAIn, MemIn, BusBIn;
  input [4:0] RwIn;

  output [1:0] RegWriteSrcOut;
  output RegWriteOut;
  output [31:0] ALUOut, AdderAOut, MemOut, BusBOut;
  output [4:0] RwOut;
  
  reg [1:0] RegWriteSrcOut;
  reg RegWriteOut;
  reg [31:0] ALUOut, AdderAOut, MemOut, BusBOut;
  reg [4:0] RwOut;

  always @(negedge CLK)
    begin
      RegWriteSrcOut <= RegWriteSrcIn;
      RegWriteOut <= RegWriteIn;
      ALUOut <= ALUIn;
      AdderAOut <= AdderAIn;
      MemOut <= MemIn;
      BusBOut <= BusBIn;
      RwOut <= RwIn;
    end
endmodule
